Ebook Digital design (5th edition): Part 2
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Ebook Digital design (5th edition): Part 2
Chapter 6Registers and Counters6.1 REGISTERSA clocked sequential circuit consists of a group of flip-flops and combinational gates.The flip-flops are Ebook Digital design (5th edition): Part 2 essential because, in their absence, the circuit reduces to a purely combinational circuit (provided that there is no feedback among the gates). A circuit with flip-flops is considered a sequential circuit even in the absence of combinational gates. Circuits that include flip-flops are usually clas Ebook Digital design (5th edition): Part 2sified by the function they perform rather than by the name of the sequential circuit. Two such circuits are registers and counters.A register is a grEbook Digital design (5th edition): Part 2
oup of flip-flops, each one of which shares a common clock and is capable of storing one bit of information. An H-bit register consists of a group of Chapter 6Registers and Counters6.1 REGISTERSA clocked sequential circuit consists of a group of flip-flops and combinational gates.The flip-flops are Ebook Digital design (5th edition): Part 2ain data-processing tasks In its broadest definition, a register consists of a group of flip-flops together with gates that affect their operation. The flip-flops hold the binary information, and the gates determine how the information is transferred into the register.A counter is essentially a regi Ebook Digital design (5th edition): Part 2ster that goes through a predetermined sequence of binary states. The gates in the counter are connected in such a way as to produce the prescribed seEbook Digital design (5th edition): Part 2
quence of states. Although counters are a special type of register, it is common to differentiate them by giving them a different name.Various types oChapter 6Registers and Counters6.1 REGISTERSA clocked sequential circuit consists of a group of flip-flops and combinational gates.The flip-flops are Ebook Digital design (5th edition): Part 2ster constructed with four D-type flip-flops to form a four-bit data storage register. Tile common clock input triggers all flip-flops on the positive edge of each pulse, and the binary data available at the four inputs are transferred into the register. The value of (/3. /2. /|. /(>) immediately be Ebook Digital design (5th edition): Part 2fore the clock edge determines the value of (A3.A2. A |. A(|) after the clock edge.Tile four255256Chapter 6 Registers and CountersFIGURE 6.1Four-bit rEbook Digital design (5th edition): Part 2
egisteroutputs can be sampled at any time to obtain the binary information stored in the register. The input Clear_h goes to the active-low R (reset) Chapter 6Registers and Counters6.1 REGISTERSA clocked sequential circuit consists of a group of flip-flops and combinational gates.The flip-flops are Ebook Digital design (5th edition): Part 2r to all 0’s prior to its clocked operation. The R inputs must be maintainedSection 6.1 Registers 257at logic 1 (i.e..de-asserted) during normal clocked operation. Note that, depending on the flip-flop, cither Clear. Clear_b. reset, or reset J) can be used to indicate the transfer of the register to Ebook Digital design (5th edition): Part 2 an all 0’s stale.Register with Parallel LoadRegisters with parallel load are a fundamental building block in digital systems. It is important that yoEbook Digital design (5th edition): Part 2
u have a thorough understanding of their behavior. Synchronous digital systems have a master clock generator that supplies a continuous train of clockChapter 6Registers and Counters6.1 REGISTERSA clocked sequential circuit consists of a group of flip-flops and combinational gates.The flip-flops are Ebook Digital design (5th edition): Part 2 parts of the system. A separate control signal must be used to decide which register operation will execute at each clock pulse, llie transfer of new information into a register is referred to as loading or updating the register. If all the bits of the register arc loaded simultaneously with a comm Ebook Digital design (5th edition): Part 2on clock pulse, we say that the loading is done in parallel. A clock edge applied to the c inputs of the register of Fig. 6.1 will load all four inputEbook Digital design (5th edition): Part 2
s in parallel. In this configuration, if the contents of the register must be left unchanged, the inputs must be held constant or the clock must be inChapter 6Registers and Counters6.1 REGISTERSA clocked sequential circuit consists of a group of flip-flops and combinational gates.The flip-flops are Ebook Digital design (5th edition): Part 2an be inhibited from reaching the register by controlling the clock input signal w ith an enabling gate. However, inserting gates into the clock path is ill advised because it means that logic is performed w ith clock pulses.The insertion of logic gates produces uneven propagation delays between the Ebook Digital design (5th edition): Part 2 master clock and the inputs of flip-flops.To fully synchronize the system, we must ensure that all clock pulses arrive at the same time anywhere in tEbook Digital design (5th edition): Part 2
he system, so that all flip-flops trigger simultaneously. Performing logic with clock pulses inserts variable delays and may cause the system to go ouChapter 6Registers and Counters6.1 REGISTERSA clocked sequential circuit consists of a group of flip-flops and combinational gates.The flip-flops are Ebook Digital design (5th edition): Part 2e c inputs of the flip-flops. This creates the effect of a gated clock, but without affecting the clock path of the circuit.A four-bit data-storagc register with a load control input that is directed through gales and into the Ỉ.) inputs of the flip-flops is shown in Fig. 6.2. Ihe additional gates i Ebook Digital design (5th edition): Part 2mplement a two-channel mux whose output dr ives the input to the register with cither the data bus or the output of the register.The load input to theEbook Digital design (5th edition): Part 2
register determines the action to be taken with each clock pulse. When the load input is 1. the data at the four external inputs arc transferred intoChapter 6Registers and Counters6.1 REGISTERSA clocked sequential circuit consists of a group of flip-flops and combinational gates.The flip-flops are Ebook Digital design (5th edition): Part 2s, lhe feedback connection from output to input is necessary because a L) flip-flop does not have a "no change" condition. With each clock edge, the D input determines the next state of the register. To leave the output unchanged, it is necessary to make the D input equal to the present value of the Ebook Digital design (5th edition): Part 2 output (i.e.. the output circulates to the input at each clock pulse).The clock pulses arc applied to the c inputs w ithout interruption.The load inpEbook Digital design (5th edition): Part 2
ut determines whether the next pulse will accept new information or leave the information in the register intact. The transfer of information from theChapter 6Registers and Counters6.1 REGISTERSA clocked sequential circuit consists of a group of flip-flops and combinational gates.The flip-flops are Ebook Digital design (5th edition): Part 2FIGURE 6.2Four-bit register with parallel load6.2 SHIFT REGISTERSA register capable of shifting the binary information held in each cell to its neighboring cell, in a selected direction, is called a shift register. The logical configuration of a shift register consists of a chain of flip-flops in ca Ebook Digital design (5th edition): Part 2scade, with the output of one flip-flop connected to the input of the next flip-flop. All flip-flops receive common clock pulses, which activate the sEbook Digital design (5th edition): Part 2
hift of data from one stage to the next.Tile simplest possible shift register is one that uses only flip-flops, as shown in Fig. 6.3. The output of a Chapter 6Registers and Counters6.1 REGISTERSA clocked sequential circuit consists of a group of flip-flops and combinational gates.The flip-flops are Ebook Digital design (5th edition): Part 2fts the contents of theSection 6.2 Shift Registers 259FIGURE 6.3Four-bit shift registerregister one bit position to the right. The configuration does not support a left shift. The serial input determines what goes into the leftmost flip-flop dining the shift. The serial output is taken from the outp Ebook Digital design (5th edition): Part 2ut of the rightmost flip-flop. Sometimes it is necessary to control the shift so that it occurs only with certain pulses, but not with others. As withEbook Digital design (5th edition): Part 2
the data register discussed in the previous section, the clock's signal can be suppressed by gating the clock signal to prevent the register from shiChapter 6Registers and Counters6.1 REGISTERSA clocked sequential circuit consists of a group of flip-flops and combinational gates.The flip-flops are Ebook Digital design (5th edition): Part 2hanged, but recirculating the output of each register cell back through a two-channel mux whose output is connected to the input of the cell. When the clock action is not suppressed, the other channel of the mux provides a datapath to the cell.It will be shown later that the shift operation can be c Ebook Digital design (5th edition): Part 2ontrolled through the D inputs of the flip-flops rather than through the clock input. If. however, the shift register of Fig. 6.3 is used, the shift cEbook Digital design (5th edition): Part 2
an be controlled with an input by connecting the clock through an AND gate. This is not a preferred practice! Note that the simplified schematics do nChapter 6Registers and Counters6.1 REGISTERSA clocked sequential circuit consists of a group of flip-flops and combinational gates.The flip-flops are Ebook Digital design (5th edition): Part 2al mode when infoi mation is transferred and manipulated one bit at a time. Information is transferred one bit at a time by shifting the bits out of the source register and into the destination register. This type of transfer is in contrast to parallel transfer, whereby all the bits of the register Ebook Digital design (5th edition): Part 2are transferred at the same time.The serial transfer of information from register A to register B is done with shift registers, as shown in the blockEbook Digital design (5th edition): Part 2
diagram of Fig. 6.4(a). The serial output (SO) of register A is connected to the serial input (SI) of register B. To prevent the loss of information sGọi ngay
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