UVM Verification of an SPI Master Core
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UVM Verification of an SPI Master Core
Rochester Institute of TechnologyRIT Scholar WorksTheses43221UVM Verification of an SPI Master CoreDeepak Siddharth Parthipandp9040@rit.eduFollow this UVM Verification of an SPI Master Cores and additional works at: httpsV/scholarworks rit.edu/thesesRecommended CitationParthipan, Deepak Siddharth, 'UVM Verification of an SPI Master Core’ (2018). Thesis. Rochester Institute of Technology. Accessed fromThis Masters Project Is brought to you for free and open access by RIT Scholar Works. UVM Verification of an SPI Master Core It has been accepted for Inclusion in Theses by an authorized administrator of RIT Scholar Works. For more Information, please contact ritscholaworksUVM Verification of an SPI Master Core
tjrit.edu.UVM VERIFICATION OF AN SPI MASTER COREbyDcepak Siddharth ParthipanGraduate PaperSubmitted in partial fulfillment of the requirements for theRochester Institute of TechnologyRIT Scholar WorksTheses43221UVM Verification of an SPI Master CoreDeepak Siddharth Parthipandp9040@rit.eduFollow this UVM Verification of an SPI Master Cored Microelectronic EngineeringDr. Sohail A. Dianat. ProfessorDepartment Head. Department of Electrical and Microelectronic EngineeringDepartment of Electrical and Microelectronic Engineering Kate Gleason College of Engineering Rochester Institute of Technology Rochester. New YorkMay. 2018https://khot UVM Verification of an SPI Master Corehuvien.corT!1 would like to dedicate this work to my family, my father Parthipan Kempanna Gowder. my mother Malarmathy Parrhipan, my sister VaishnaviUVM Verification of an SPI Master Core
Parrhipan, and friends for their love and support during my thesis.DeclarationI hereby state that except where explicit references are made to the worRochester Institute of TechnologyRIT Scholar WorksTheses43221UVM Verification of an SPI Master CoreDeepak Siddharth Parthipandp9040@rit.eduFollow this UVM Verification of an SPI Master Coreer qualification in this, or any other University. This UVM Verification of an SPI Master Core Graduate Paper is the result of my work and not a collaborative work, except where explicit references arc mentioned.Deepak Siddharth ParthipanMay. 2018AcknowledgementsI would like to (hank my advisor. Pro UVM Verification of an SPI Master Corefessor Mark A. Indovina. for his support, guidance, feedback, and encouragement which helped in the successful completion of my graduate research.AbstUVM Verification of an SPI Master Core
ractIn today’s world, more and more functionalities in the form of IP cores are integrated into a single chip or soc. System-level verification of sucRochester Institute of TechnologyRIT Scholar WorksTheses43221UVM Verification of an SPI Master CoreDeepak Siddharth Parthipandp9040@rit.eduFollow this UVM Verification of an SPI Master Corependent, scalable, and reusable verification components. The System Verilog language is based on object-oriented principles and is the most promising language to develop a complete verification environment with functional coverage, constrained random testing and assertions. The Universal Verificatio UVM Verification of an SPI Master Coren Methodology, written in System Verilog, is a base class library of reusable verification components. This paper discusses a Universal Verification MUVM Verification of an SPI Master Core
ethodology based environment for testing a Wishbone compliant SPI master controller core. A multi-layer testbench was developed which consists of a WiRochester Institute of TechnologyRIT Scholar WorksTheses43221UVM Verification of an SPI Master CoreDeepak Siddharth Parthipandp9040@rit.eduFollow this UVM Verification of an SPI Master Coreog an the UVM library. Later, constrained random testing using vectors driven into the DUT for higher functional coverage is discussed. The verification results shows the effectiveness and feasibility of the proposed verification environment. UVM Verification of an SPI Master CoreRochester Institute of TechnologyRIT Scholar WorksTheses43221UVM Verification of an SPI Master CoreDeepak Siddharth Parthipandp9040@rit.eduFollow thisGọi ngay
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