A Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate Arrays
➤ Gửi thông báo lỗi ⚠️ Báo cáo tài liệu vi phạmNội dung chi tiết: A Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate Arrays
A Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate Arrays
NORTHWESTERN UNIVERSITYA Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate ArraysA DISSERTATIONSUBMITTED TO THE GRA A Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate ArraysADUATE SCHOOL IN PARTIAL FULFILLMENTS OF THE REQUIREMENTSfor (he degreeDOCTOR OF PHILOSOPHYField of Electrical and Computer EngineeringByDavid c. ZaretskyEVANSTON, ILLINOIS38687AbstractA METHODOLOGY 1 OR TRANSLATING SCHEDULED son WARE BINARIES ONIO FIELD PROGRAMMABLE GATE ARRAYSDAVID c. ZARETSKYRece A Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate Arraysnt advances in embedded communications and control systems are pushing the computational limits OÍ DSP applications, driving the need for hardware/sofA Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate Arrays
tware codesign systems. This dissertation describes the development and architecture of the FREEDOM compiler that translates DSP software binaries to NORTHWESTERN UNIVERSITYA Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate ArraysA DISSERTATIONSUBMITTED TO THE GRA A Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate Arraysrdware, and described an array of optimizations that were implemented in the compiler. Our balanced scheduling and operation chaining techniques show even greater improvements in performance. Our resource sharing optimization generates templates of reoccurring patterns in a design to reduce resource A Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate Arrays utilization. Our structural extraction technique identifies structures in a design for partitioning as part of a hardware/softwarc co-dcsign. These cA Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate Arrays
oncepts were tested in a case study of an MPF.G-4 decoder. Results indic ate speedups between 14-G7x in terms of cycles and 6-22X in terms of time forNORTHWESTERN UNIVERSITYA Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate ArraysA DISSERTATIONSUBMITTED TO THE GRA A Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate Arraysfficient method for high-level synthesis.iiiAcknowledgementsI wish (0 thank my advisor, Prith Banerjee, for allowing me the opportunity to work under his guidance as a graduate student at Northwestern University. His support and encouragement has led to the accomplishments of my work as described in A Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate Arrays this dissertation. I would also like to thank my secondary advisor, Robert Dick, who was a tremendous help in much of my research. His guidance and iA Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate Arrays
nput was immeasurable.I wish to thank Professors Prith Banerjee, Robert Dick, Seda Ogrenci Memik, and Hai Zhou for participating on the final examinatNORTHWESTERN UNIVERSITYA Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate ArraysA DISSERTATIONSUBMITTED TO THE GRA A Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate Arraysour helpful insights in the different aspects of the project that were invaluable to the successful completion of this dissertation. I wish to also thank my fellow colleagues at Northwestern University who have shared research ideas and with whom I have collaborated.A special thank you to Kees Visse A Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate Arraysrs, Robert Turney, and Paul Schumacher at Xilinx Research Labs for providing me with the MPEG-4 source code to be used in my Ph.D. research and in thiA Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate Arrays
s dissertation.Finally, I wish to thank my parents for teaching me... the sky is the limit!ivTable of ContentsAbstract iiiAcknowledgements............NORTHWESTERN UNIVERSITYA Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate ArraysA DISSERTATIONSUBMITTED TO THE GRA A Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate Arrays.................................ixList of Figures......................................................xiIntroduction..........................................................11.1Binary to Hardware Translation...................................31.2Texas Instruments TMS320C6211 DSP Design Flow...... A Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate Arrays..............61.3Xilinx Virtex II FPGA Design Flow................................81.4Motivational Example...........................................A Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate Arrays
.111.5Dissertation Overview'..........................................12NORTHWESTERN UNIVERSITYA Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate ArraysA DISSERTATIONSUBMITTED TO THE GRANORTHWESTERN UNIVERSITYA Methodology For Translating Scheduled Software Binaries onto Field Programmable Gate ArraysA DISSERTATIONSUBMITTED TO THE GRAGọi ngay
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